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[ak4426] ms1176-e-02 2011/03 - 1 - ak4426 192khz 24-bit stereo ? dac with 2vrms output general description the ak4426 is a 5v 24-bit stereo dac with an int egrated 2vrms output buffer. a charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2vrms output. using akm?s multi bit modulator architecture, t he ak4426 delivers a wide dynamic range while preserving linearity for improved thd+n perform ance. the ak4426 integrates a combination of sw itched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. the 24-bit word length and 192khz sampling rate make this part ideal for a wide range of consumer audio applications, such as dvd, av re ceiver system and set-top boxes. the ak4426 is offered in a space saving 16pin tssop package. features ? sampling rate ranging from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24-bit 8 times fir digital filter ? switched-capacitor filter with high tolerance to clock jitter ? single ended 2vrms output buffer ? digital de-emphasis filter: 32khz, 44.1khz or 48khz ? soft mute ? digital attenuator (linear 256 step) ? control i/f: i 2 c-bus ? audio i/f format: 24bit msb justified, 24/20/16 lsb justified or i 2 s compatible ? master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (normal speed mode) 128fs, 192fs, 256fs or 384fs (double speed mode) 128fs, 192fs (quad speed mode) ? thd+n: -91db ? dynamic range: 106db ? automatic power-on reset circuit ? power supply: +4.5 +5.5v ? ta = -40 to 85 c ? small package: 16pin tssop (6.4mm x 5.0mm)
[ak4426] lrck bick sdti audio data interface mclk modulator a outl 8x interpolator scf lpf a outr a v dd v ss2 de-emphasis control control interface clock divider modulator 8x interpolator scf lpf charge pump cp cn v ee v ss1 v dd 1 1 cad0 scl sda block diagram ms1176-e-02 2011/03 - 2 -
[ak4426] ordering guide ak4426vt -40 +85 c 16pin tssop (0.65mm pitch) AKD4426 evaluation board for ak4426 pin layout 6 5 4 3 2 1 vdd mclk sdti bick lrck cad0 7 sda 8 vss1 cp cn vee aoutl vss2 avdd aoutr ak4426 top view 11 12 13 14 15 16 10 9 scl ms1176-e-02 2011/03 - 3 -
[ak4426] pin/function no. pin name i/o function 1 vdd - digital circuit and charge pump circuit power supply pin: 4.5v 5.5v 2 mclk i master clock input pin an external ttl clock must be input on this pin. 3 bick i audio serial data clock pin 4 sdti i audio serial data input pin 5 lrck i l/r clock pin 6 cad0 i chip address 0bit 7 scl i control clock input pin 8 sda i/o control data input/output pin 9 aoutr o rch analog output pin when power down, outputs vss(0v, typ). 10 avdd - analog block power supply pin: 4.5v 5.5v 11 vss2 - ground pin2 12 aoutl o lch analog output pin when power down, outputs vss(0v, typ). 13 vee o negative voltage output pin connect to vss1 with a 1.0 f capacitor which is low esr (equivalent series resistance) over all temperatur e range. when this capacitor has the polarity, the positive polarity pin must be connected to the vss1 pin. non polarity capacitors can also be used. 14 cn i negative charge pump capacitor terminal pin connect to cp with a 1.0 f capacitor which is low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin must be connect ed to the cp pin. non polarity capacitors can also be used. 15 cp i positive charge pump capacitor terminal pin connect to cn with a 1.0 f capacitor which is low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin must be connect ed to the cp pin. non polarity capacitors can also be used. 16 vss1 - ground pin1 note: all input pins except for the cn pin should not be left floating. ms1176-e-02 2011/03 - 4 -
[ak4426] absolute maximum ratings (vss1=vss2=0v; note 1 ) parameter symbol min max units power supply vdd cvdd -0.3 -0.3 +6.0 +6.0 v v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. vss1, vss2 connect to the same analog ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 1 ) parameter symbol min typ max units power supply vdd avdd +4.5 +5.0 vdd +5.5 v note 3. avdd should be equal to vdd *akm assumes no responsibility for the usage beyond the conditions in this datasheet. ms1176-e-02 2011/03 - 5 -
[ak4426] analog characteristics (ta = 25 c; vdd=avdd = +5.0v; fs = 44.1 khz; bick = 64fs; signal frequency = 1 khz; 24bit input data; measurement frequency = 20hz 20khz; r l 5k ) parameter min typ max units resolution 24 bits dynamic characteristics ( note 4 ) fs=44.1khz, bw=20khz -91 -84 db fs=96khz, bw=40khz -91 - db thd+n (0dbfs) fs=192khz, bw=40khz -91 - db dynamic range (-60dbfs with a-weighted. ( note 5 ) 100 106 db s/n (a-weighted. ( note 6 ) 100 106 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy dc offset (at output pin) -5 0 +5 mv gain drift 100 - ppm/ c output voltage ( note 7 ) 2.05 2.2 2.35 vrms load capacitance ( note 8 ) 25 pf load resistance 5 k power supplies power supply current: ( note 9 ) normal operation (fs 96khz) normal operation (fs=192khz) power-down mode ( note 10 ) 24 27 10 36 40 100 ma ma a note 4. measured by audio precision (system two). refer to the evaluation board manual. note 5. 98db for 16bit input data note 6. s/n does not depend on input data size. note 7. full-scale voltage (0db). output voltage is proportional to the voltage of avdd, aout (typ.@0db) = 2.2vrms avdd/5. note 8. in case of driving capacitive load, inset a resistor between the output pin and the capacitive load. note 9. the current into vdd and avdd. note 10. all digital inputs including clock pins (mclk, bick and lrck) are fixed to vss1(vss2) or vdd(avdd). ms1176-e-02 2011/03 - 6 -
[ak4426] sharp roll-off filter characteristics (ta = 25 c; vdd=avdd = +4.5 +5.5v; fs = 44.1 khz; dem = off; slow = ?0?) parameter symbol min typ max units digital filter passband 0.05db ( note 11 ) ?6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 11 ) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 12 ) gd - 19.3 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.05 0.05 0.05 - - - db db db note 11. the passband and stopband frequencie s scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 12. calculated delay time caused by digital filte r. this time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. slow roll-off filter characteristics (ta = 25 c; vdd = avdd = +4.5 +5.5v; fs = 44.1khz; dem = off; slow = ?1?) parameter symbol min typ max units digital filter passband 0.04db ( note 13 ) -3.0db pb 0 - 18.2 8.1 - khz khz stopband ( note 13 ) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay ( note 12 ) gd - 19.3 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0/-5 +0/-4 +0/-5 - - - db db db note 13. the passband and stopband frequencie s scale with fs(system sampling rate). for example, pb=0.185fs (@ 0.04db), sb=0.888fs. ms1176-e-02 2011/03 - 7 -
[ak4426] dc characteristics (ta = 25 c; vdd=avdd = +4.5 +5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v input leakage current iin - - 10 a switching characteristics (ta = 25 c; vdd=avdd = +4.5 +5.5v) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 30 11.2896 36.864 70 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 32 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high bick ? ? to lrck edge ( note 14 ) lrck edge to bick ? ? ( note 14 ) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128f sn 1/64fs d 1/64fs q 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns control interface timing (i2c bus) ( note 15 ) scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 16 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 14. bick rising edge must not occur at the same time as lrck edge. note 15. i 2 c-bus is a trademark of nxp b.v. note 16. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. ms1176-e-02 2011/03 - 8 -
[ak4426] timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 1. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 2. serial interface timing ms1176-e-02 2011/03 - 9 -
[ak4426] thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 3. i 2 c bus mode timing ms1176-e-02 2011/03 - 10 -
[ak4426] operation overview system clock the external clocks required to operate the ak4426 are mc lk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting m ode (acks = ?0?: register 00h), the sampling speed is set by dfs0/1 ( table 1 ). the frequency of mclk at each sampling speed is set automatically. ( table 2 ) when the power applied, the ak4426 is in au to setting mode. in auto setting mode (acks = ?1?: default), as mclk frequency is detected automatically ( table 3 ) and the internal master clock becomes the appropriate frequency ( table 4 ), it is not necessary to set dfs0/1. the ak4426 is automatically placed in power saving mode when mclk, lrck and bick stop during normal operation mode, and the analog output is forced to 0v(typ). when mclk, lrck and bick are input again, the ak4426 is powered up. after power-up, the ak4426 is in the pow er-down mode until mclk, lrck and bick are input. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz~48khz (default) 0 1 double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) lrck (khz) mclk (mhz) bick (mhz) dfs1 dfs0 sampling speed fs 128fs 192fs 256fs 384f s 512fs 768fs 1152fs 64fs 0 0 32.0 - - 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480 0 0 44.1 - - 11.2896 16.9344 22.5792 33.8688 - 2.8224 0 0 normal 48.0 - - 12.2880 18.4320 24.5760 36.8640 - 3.0720 0 1 88.2 11.2896 16.9344 22.5792 33.8688 - - - 5.6448 0 1 double 96.0 12.2880 18.4320 24.5760 36.8640 - - - 6.1440 1 0 176.4 22.5792 33.8688 - - - - - 11.2896 1 0 quad 192.0 24.5760 36.8640 - - - - - 12.2880 table 2. system clock example (manual setting mode) mclk sampling speed 1152fs normal (fs=32khz only) 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 3. sampling speed(auto setting mode: default) ms1176-e-02 2011/03 - 11 -
[ak4426] lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 32.0khz 8.192 12.288 44.1khz 11.2896 16.9344 48.0khz 12.288 18.432 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - quad 192.0khz 24.5760 36.8640 - - - - - table 4. system clock example (auto setting mode) when mclk= 256fs/384fs, the ak4425 supports sampling rate of 32khz~96khz in auto setting mode ( table 4 ). but, when the sampling rate is 32khz~48kh z, dr and s/n will degrade as co mpared to when mclk= 512fs/768fs. mclk dr,s/n 256fs/384fs 103db 512fs/768fs 106db table 5. relationship between mclk frequency and dr, s/n (fs= 44.1khz) (auto setting mode) audio serial interface format the audio data is shifted in via the sdti pin using the bick and lrck inputs. the dif2-0 bit can select within five serial data modes as shown in table 6 . in all modes the serial data is msb-first, two?s complement format and it is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti format bick figure 0 0 0 0 16bit lsb justified 32fs figure 4 1 0 0 1 20bit lsb justified 40fs figure 5 2 0 1 0 24bit msb justified 48fs figure 6 (default) 3 0 1 1 24bit i 2 s compatible 48fs figure 7 4 1 0 0 24bit lsb justified figure 5 48fs table 6. audio data format in serial control mode ms1176-e-02 2011/03 - 12 -
[ak4426] sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 01 4 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 4. mode 0 timing sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 5. mode 1/4 timing lrck bick ( 64fs ) sdti 02 2 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 22 4 23 30 22 1 0 don?t care 23 22 23 figure 6. mode 2 timing ms1176-e-02 2011/03 - 13 -
[ak4426] lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 22 4 23 25 22 1 0 don?t care 23 23 figure 7. mode 3 timing ms1176-e-02 2011/03 - 14 -
[ak4426] de-emphasis filter a digital de-emphasis filter is availabl e for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 7. de-emphasis filter control (normal speed mode) analog output block the internal negative power supply generation circuit ( figure 8 ) provides a negative power supply for the internal 2vrms amplifier. it allows the ak4426 to output an audio signal centered at vss (0v, typ) as shown in figure 9 . the negative power generation circuit ( figure 8 ) needs 1.0uf low esr (equivalent series resistance) capacitors (ca, cb). if this capacitor is polarized, the positive polarity pin should be connected to the cp and vss1 pins. this circuit operates by clocks generated from mclk. when mclk stops, the ak4426 is placed in the rese t mode automatically and the analog outputs settle to vss (0v, typ). vdd charge pump cp cn vss1 vee 1uf 1uf negative power a k4426 (+) cb ca (+) figure 8. negative power generation circuit a outr a k4426 (aoutl) 0v 2.2vrms figure 9. audio signal output ms1176-e-02 2011/03 - 15 -
[ak4426] output volume the ak4426 includes channel independent digital output volumes (att) with 256 levels at linear step including mute. these volumes are in front of the dac and can attenuate the input data from 0db to ?48db and mute. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. the transition time of 1 level and all 256 levels is shown in table 8 . transition time sampling speed 1 level 255 to 0 normal speed mode 4lrck 1020lrck double speed mode 8lrck 2040lrck quad speed mode 16lrck 4080lrck table 8. att transition time soft mute operation soft mute operation is performed in digital domain. when the smute bit goes to ?1?, the output signal is attenuated by - during att_data att transition time ( table 8 ) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation att level - aout gd gd (1) (2) (3) (1) notes: (1) att_data att transition time ( table 8 ). for example, in normal speed mode, this time is 1020lrck cycles (1020/fs) at att_data=255. (2) the analog output corresponding to the digital input has group delay, gd. (3) if the soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level by the same cycle. figure 10. soft mute function ms1176-e-02 2011/03 - 16 -
[ak4426] system reset the ak4426 is in power down mode upon power-up. the mlck should be input after the power supplies are ramped up. the ak4426 is in power-down mode until lrck are input. t w<20ms mclk low power supply (vdd, avdd) charge pump circuit vee pin power down 0.8xvdd 0.3v power-up 0v reset 20 s (3) (1) 50ms(max) ) internal reset reset release (2) time a audio circuit power-up 2, 3 lrck clocks (5) d/a out (analog) mute ( d/a out ) d/a in (digital) ?0? data 0v a ctive ( d/a out ) (4) notes: (1) the ak4426 includes an internal power on reset circuit which is used to reset the digital logic into a default state after power up. therefore, the power supply voltage must reach 80% vdd from 0.3v in less than 20msec. (2) register writings are valid after 50ms (max). (3) when internal reset is made, approximately 20us after a mclk input, the internal analog circuit is powered-up. (4) the digital circuit and charge pump circuit are powered-up in 2, 3 lrck cycle when the analog circuit is powered-up. (5) the charge pump counter starts after the charge pump circuit is powered-up. the dac outputs a valid analog signal after time a. time a = 1024/(fs x 16): normal speed mode time a = 1024/(fs x 8): double speed mode time a = 1024/(fs x 4): quad speed mode figure 11. system reset diagram ms1176-e-02 2011/03 - 17 -
[ak4426] reset function when the mclk, lrck or bick stops, the ak4426 is placed in reset mode and its analog outputs are set to vss (0v, typ). when the mclk, lrck and bick are restarted, the ak4426 returns to normal operation mode. normal operation internal state reset normal operation gd d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (2) vss (3) mclk or bic k or lrck sto p (4) (4) (1) notes: (1) clocks (mclk, bick, lrck) can be stopped in the reset mode (mclk or lrck is stopped). (2) digital data can be stopped. the click noise after mclk and lrck are input again can be reduced by inputting the ?0? data during this period. (3) the analog output corresponding to a specific digital input has group delay (gd). (4) no audible click noise o ccurs under normal conditions. figure 12. reset timing example ms1176-e-02 2011/03 - 18 -
[ak4426] mode control interface i 2 c-bus control mode 1. write operations figure 13 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 17 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit which is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001000?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets this device address bit ( figure 14 ). if the slave address match that of the ak4426 and r/w bit is ?0?, the ak4426 generates an acknowledge and the write operation is executed. if r/w bit is ?1?, the ak4426 does not answer any acknowledge ( figure 17 ). the second byte consists of the address for control registers of the ak4426. the format is msb first, and those most significant 6-bits are fixed to zeros ( figure 15 ). the data after the second byte contain control data. the format is msb first, 8bits ( figure 16 ). the ak4426 generates an acknowledge after each byte is receive d. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 17 ). the ak4426 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the ak4426 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after the receipt of each data, the internal address counter is incremented by one, and the ne xt data is taken into next address au tomatically. if the address exceeds 04h prior to generating the stop condition, the addr ess counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 19 ) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 13. data transfer sequence at i 2 c-bus mode 0 0 1 0 0 0 cad0 r/w figure 14. the first byte ( the cad0 should match with cad0 pin) 0 0 0 0 0 0 a1 a0 figure 15. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 16. byte structure after the second byte ms1176-e-02 2011/03 - 19 -
[ak4426] scl sda stop condition start condition s p figure 17. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 18. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 19. bit transfer on the i 2 c-bus ms1176-e-02 2011/03 - 20 -
[ak4426] register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn 01h control 2 0 0 slow dfs1 dfs0 dem1 dem0 smute 02h control 3 rrst 0 0 invl invr 0 0 0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 notes: do not write any data to the register over 05h directly. when rstn bit goes ?0?, the only internal timing is reset and the registers are not initialized to their default values. all data can be written to the register even if pw or rstn bit is ?0?. do not write the registers within 50msec after the power supplies are fed. ms1176-e-02 2011/03 - 21 -
[ak4426] register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn default 1 0 0 0 1 0 1 1 rstn: internal timing reset control 0: reset. all registers are not initialized. 1: normal operation the click noise, which occurs when mclk frequency or dfs is changed, can be reduced by rstn bit. pw: power down control 0: power down. all registers are not initialized. 1: normal operation dif2-0: audio data interface formats ( table 6 ) default: ?010?, mode 2 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected au tomatically at acks bit ?1?. in this case, the settings of dfs1-0 are ignored. when this bit is ?0?, dfs1-0 set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 slow dfs1 dfs0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation 1: dac outputs soft muted dem1-0: de-emphasis response ( table 7 ) default: ?01?, off dfs1-0: sampling speed control 00: normal speed mode 01: double speed mode 10: quad speed mode when changing between normal/double speed mode and quad speed mode, some click noise occurs. slow: slow roll-off filter enable 0: sharp roll-off filter 1: slow roll-off filter ms1176-e-02 2011/03 - 22 -
[ak4426] addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 rrst 0 0 invl invr 0 0 0 default 0 0 0 0 0 0 0 0 invr: inverting lch output polarity 0: normal output 1: inverted output invl: inverting rch output polarity 0: normal output 1: inverted output rrst: register reset 0: normal operation 1: register reset (except rrst bit) addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att = 20 log 10 (att_data / 255) [db] 00h: mute ms1176-e-02 2011/03 - 23 -
[ak4426] system design figure 20 shows the system connection diagram. an evaluation boa rd (AKD4426) is available for fast evaluation as well as suggestions for peripheral circuitry. 24bit audio data 64fs master clock analog ground digital ground + p ak4426 sda cad0 lrck sdti bick mclk vdd scl aoutr avdd vss2 aoutl vee cn cp vss1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + fs 1u (1) 0.1u 10u + 0.1u 10u lch out rch out + 1u (1) analog 5.0v note: use low esr (equivalent series resistance) capacitors. when using polarized capacitors, the positive polarity pin should be connected to the cp and vss2 pin. vss1 and vss2 should be separated from digital system ground. digital input pins should not be allowed to float. figure 20. typical connection diagram ms1176-e-02 2011/03 - 24 -
[ak4426] 1. grounding and power supply decoupling vdd and avdd are supplied from the analog supply and shoul d be separated from the system digital supply. decoupling capacitors, especially 0.1 f ceramic capacitors for high frequency by pass, should be placed as near to vdd and avdd as possible. the vss1 and vss2 must be connected to the same analog ground plane. power-up sequence between vdd and avdd is not critical. 2. analog outputs the analog outputs are single-ended and centered around the v ss (ground) voltage. the output signal range is typically 2.2vrms (typ @vdd=5v). the internal switched-capacitor filter (scf) and con tinuous-time filter (ctf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. using single a 1 st -order lpf ( figure 21 ) can reduce noise beyond the audio passband. aout 470 2.2nf ak4426 2.2vrms (typ) analog out (fc = 154khz, gain = -0.28db @ 40khz, gain = -1.04db @ 80khz) figure 21. external 1 st order lpf circuit example1 ms1176-e-02 2011/03 - 25 -
[ak4426] package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatme nt: solder (pb free) plate ms1176-e-02 2011/03 - 26 -
[ak4426] marking akm 4426vt xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4426vt 4) asahi kasei logo date (yy/mm/dd) revision history revision reason page contents 10/06/07 00 first edition 10/07/22 01 error correction 19-20 mode control interface the description was corrected. 11/03/01 02 error correction 25 1. grounding and power supply decoupling the description was changed. ms1176-e-02 2011/03 - 27 -
[ak4426] important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. ms1176-e-02 2011/03 - 28 -

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